The invention relates to a method of manufacturing a field-effect transistor substantially consisting of organic materials.
The invention also relates to a field-effect transistor substantially consisting of organic materials.
The invention further relates to an integrated circuit (IC) comprising such a field-effect transistor (FET).
An integrated circuit comprising field-effect transistors substantially consisting of organic materials, in short organic field-effect transistors, is well suited for those electronic applications where using an integrated circuit manufactured using silicon technology would be prohibitively expensive. Examples include electronic bar codes.
As is well known by those skilled in the art, if an IC is to perform its task, it is imperative that the integrated logic gates, such as invertors, NOR and NAND gates, attain voltage amplification at the operating voltage. In order to attain voltage amplification, each individual field-effect transistor must be operated in a saturated regime, which is the regime where the channel transconductance exceeds the channel conductance.
A method of the type mentioned in the opening paragraph, which provides an organic FET satisfying said condition for voltage amplification is known from an article by Garnier et al. published in Science, vol. 265 (1994), pp. 1684-1686. In said known method a 1.5 xcexcm thick polyester film is framed and is printed on both sides with a graphite-filled polymer ink, so as to form a 10 xcexcm thick gate electrode on the one side and a source and drain electrode on the other side. Between the source and drain a 40 nm semiconducting sexithiophene layer is then deposited using flash evaporation.
A disadvantage of the known method is that the organic FETs provided by the method satisfy the condition for voltage amplification only at rather high (negative) source drain voltages. Typically, the difference is 30 V or higher. For many electronic applications, such as battery operated applications, such a voltage is too high. Also, the method is not very practical, not least because it involves framing and printing on a layer of only 1.5 xcexcm. Such a thin film is very fragile and easily ruptures while being handled, leading to a defective device.
An object of the invention is, inter alia, to provide a novel method of manufacturing a field-effect transistor substantially consisting of organic materials. The novel method should enable, in a practical manner, the manufacture of an organic FET satisfying the condition of voltage amplification at a source drain voltage difference significantly less than 30 V, in particular less than 10 V.
The object of the invention is achieved by a method of manufacturing a field-effect transistor substantially consisting of organic materials on a substrate surface, said method comprising the steps of:
providing an electrically insulating substrate surface,
applying an organic first electrode layer accommodating a source and drain electrode and demonstrating a patchwork pattern of electrically insulating and conducting areas,
applying an organic semiconducting layer preferably of a thickness so selected that the condition for voltage amplification is satisfied at source drain voltages less than 10 V, and especially,
applying an organic electrically insulating layer having a thickness less than 0.3 xcexcm,
applying an organic second electrode layer accommodating a gate electrode.
Using the method in accordance with the invention, it is possible to manufacture FETs satisfying the condition of voltage amplification at source drain voltages below 10 V, for example, about 2.5 V.
The invention is based on the insight that a very thin electrically insulating layer, that is a layer having a thickness of 0.3 xcexcm or less, is required if an organic FET is to satisfy the condition of voltage amplification at a source drain voltage difference of less than 10 V. It is further based on the insight that such a thin insulating layer can only be obtained in a practical manner if (in contrast to the known method in which the insulating layer is used as a substrate for depositing the electrodes) the thin insulating layer is supported by a substrate throughout the manufacture of the FET. Most conveniently, the insulating layer is applied to a surface which is substantially planar. Manufacturing the first electrode layer in the form of a patchwork pattern of electrically insulating and conducting areas provides a substantially planar surface (the difference in thickness between the insulating and conducting areas being 0.05 xcexcm or less).
The method in accordance with the invention is simple and cost effective. It involves few steps. The first and second electrode layer, as well as the insulating and semiconducting layer, can be, and preferably are, all applied from solution using coating techniques known per se, such as spin-coating, dip-coating, spray-coating, curtain-coating, silkscreen-printing, offset-printing, Langmuir Blodgett and the doctor blade technique.
The field-effect transistor obtained by employing the method in accordance with the invention operates in the usual manner. The semiconducting layer comprises an area, the channel, which interconnects the source and the drain electrode. The gate electrode is electrically insulated from the channel by means of the insulating layer and overlaps the channel. If a voltage is applied between the source and drain electrode, a current, i.e. the source drain current, will flow through the channel. By applying a gate voltage, an electric field is established across the semiconducting layer which will, depending on the polarity of both the gate voltage and the charge carriers, modify the free charge carrier distribution in the channel, thereby changing the resistivity of the channel and the source drain current. If the source drain voltage is increased while the gate voltage is kept constant, the source drain current will begin to saturate and at some point the condition of voltage amplification, i.e. the channel transconductance exceeding the channel conductance, is satisfied.
The first electrode layer comprises electrically insulating and conducting areas, which may be of any convenient shape. The source and drain electrode are accommodated by separate conducting areas. In order to increase the channel width, thus allowing more current between source and drain, the source and drain electrode are preferably interdigitated.
In order to minimize the leakage current and the voltage drop between separate conducting areas, in particular between the source and drain electrodes, the sheet resistance of the insulating areas needs to be as high as possible. A suitable sheet resistance exceeds 1010 xcexa9/square, or better 1012 xcexa9/square or better still 1013 xcexa9/square.
The specific conductivity of the conducting areas of the electrode layer is chosen such that the source drain current is substantially determined by the resistivity of the channel. A suitable specific conductivity of the conducting areas is 0.1 S/cm or better 1 S/cm or better still more than 10 S/cm.
Applying the patchwork patterned first electrode layer is for example done by applying a semiconducting polymer in an insulating state from solution, applying and patterning a photoresist layer photolithographically and introducing conducting areas by selective indiffusion of a dopant which converts locally the polymer from its insulating to a conducting state.
Preferably, the patchwork patterned first electrode layer is applied without using the elaborate technique of photolithography. This is achieved by an embodiment of the method in accordance with the invention which is characterized in that the organic first electrode is applied by performing the method steps of
applying an organic radiation-sensitive layer,
irradiating said radiation-sensitive layer according to a desired pattern, thereby forming an organic first electrode layer accommodating a source and drain electrode and demonstrating a patchwork pattern of irradiated electrically insulating and non-irradiated conducting areas.
Examples of radiation-sensitive layers which have been found effective in the context of the present invention, are disclosed in U.S. Pat. Nos. 5,427,841, 5,620,800 and 5,447,824, assigned to U.S. Philips Corporation.
Within the context of the present invention, use is preferably made of a radiation-sensitive layer comprising an electrically conducting polyaniline and a photochemical radical initiator. Surprisingly, it has been found that such a layer may be rendered radiation insensitive by a simple heat treatment at for example 110xc2x0 C. This property is very advantageous if an IC is to be manufactured, especially if multi level interconnects are required, for it allows the second (and any further) electrode layer to be patchwork patterned employing the same radiation-sensitive composition and method steps without the pattern of the first electrode layer being affected by the radiation employed in providing said second electrode layer.
Onto the first electrode layer an organic semiconducting layer is applied. Suitable semiconducting layers comprise organic compounds having an extensive conjugated system of double and/or triple bonds such as conjugated polymers (in the context of the invention, the term polymer includes oligomer) and fused (heterosubstituted) polycyclic hydrocarbons. Examples include polypyrroles, polyphenylenes, polythiophenes, polyphenylenevinylenes, poly(di)acetylenes, polyfuranes and polyanilines. As known by those skilled in the art, such compounds may be rendered semiconducting by doping with an oxidizing agent, reducing agent and/or (Bronsted) acid. It may happen that the method of preparing the semiconducting compound is such that the compound is obtained in the semiconducting state without explicitly adding a dopant, in which case the compound is said to be unintentionally doped.
In case a subsequent layer is to be provided from solution using a solvent, the semiconducting layer may swell or even dissolve into the subsequent layer before the solvent is removed, thus ruining the definition of the interface. In order to prevent this from happening, use is preferably made of an insoluble semiconducting compound obtainable from a soluble precursor compound. Examples of such compounds, viz. a polythienylenevinylene and a pentacene, are described in a publication by Brown et al. in Science, vol. 270, (1995), pp. 972-974.
Onto the semiconducting layer an organic electrically insulating layer is applied which electrically insulates the gate electrode from the semiconducting layer.
The electrically insulating layer preferably has a high capacitance so as to induce a large current between source and drain using a low gate voltage which is accomplished by using a material with a large dielectric constant and/or a small layer thickness.
In order to reduce the risk of short circuits and/or the leakage current between gate and source/drain, the thickness of the insulating layer is preferably more than 0.05 xcexcm.
Examples of suitable organic electrically insulating materials are disclosed in United States patent specification U.S. Pat. No. 5,347,144.
If a subsequent layer is applied from solution onto the electrically insulating layer, there is a risk that it swells, dissolves or mixes with the subsequent layer before the solvent has evaporated from the solution. In order to reduce this risk it has been found favourable to employ an insulating material which can be rendered insoluble by cross-linking. A preferred embodiment of the method in accordance with the invention is therefore characterized in that the organic electrically insulating layer comprises a cross-linked polymer.
A cross-linkable polymer which has been found very effective is a polyvinylphenol. It can be cross-linked by adding a cross-linking agent such as hexamethoxymethylenemelamine and heating.
The organic FET is completed by applying a second electrode layer accommodating a gate electrode. The insulating layer already being in place, the (variation in) layer thickness and the deposition process is less critical. For example, the second electrode layer can be suitably applied using the method disclosed in the article by Garnier et al. cited hereinabove, that is, printing of a graphite filled polymer ink. However, a method of manufacturing the organic FET, which is more economical and allows a higher resolution, results if the second electrode is applied in the same manner as the first electrode layer.
The method involves providing an electrically insulating substrate surface. The surface should be planar and smooth. Suitable substrates are ceramics, glass, silica or, preferably, (laminated) polymer foils such as polystyrene, polyamide, polyamide and polyester foils. If a first electrode layer comprising conductive polyaniline and a photochemical radical initiator is applied, the substrate surface preferably comprises (crosslinked) polyvinylphenol or polyvinylalcohol.
A preferred embodiment of the method in accordance with the invention is the method which comprises the additional steps of
providing an electrically insulating substrate surface,
applying, from solution, a first organic radiation-sensitive layer comprising a conductive polyaniline and a photochemical radical initiator,
irradiating said first radiation-sensitive layer according to a desired pattern, thereby forming an organic first electrode layer accommodating a source and drain electrode and demonstrating a patchwork pattern of irradiated electrically insulating and non-irradiated conducting areas,
heating the first electrode layer at a temperature sufficient to render said first electrode layer radiation-insensitive,
applying, from solution, a second organic semiconducting layer comprising a polythienylenevunylene,
applying, from solution, a cross-linkable polymer composition,
cross-linking the cross-linkable polymer composition, thereby forming an organic electrically insulating layer comprising a cross-linked polymer composition,
applying, from solution, a second organic radiation-sensitive layer comprising a conductive polyaniline and a photochemical radical initiator,
irradiating said second radiation-sensitive layer according to a desired pattern, thereby forming an organic second electrode layer accomodating a gate electrode and demonstrating a patchwork pattern of irradiated electrically insulating and non-irradiated conducting areas.
This method has been found particularly suitable in that each time a subsequent layer is applied from solution, swelling or dissolution of the preceding layer does not occur. The method moreover allows FETs having a channel length as small as 1 to 2 xcexcm to be produced in a reliable and practical manner.
The inventors have observed that if a field-effect transistor manufactured using the method in accordance the invention is operated for a long time (for minutes to hours) at high source drain voltage differences, there is a risk that the performance of the FET deteriorates to the extent that it does no longer satisfy the condition for voltage amplification at voltages below 10 V. In order to reduce this risk, a preferred embodiment of the method in accordance with the invention is characterized in that before the semiconducting layer is applied, the electrically insulating areas of the first electrode layer are removed, thereby forming a first electrode layer demonstrating a relief pattern of conducting areas.
In case the first electrode layer comprises polyaniline, removal can be achieved, for example, by dissolving selectively the electrically insulating areas in N-methylpyrrolidone.
Surprisingly, the presence of a relief pattern does not lead to a dramatic increase in leakage current or short circuits between the source (drain) and gate electrode. At least this is found to be the case if the thickness of the first electrode layer is chosen to be smaller than the thickness of the insulating layer. Apparently, a relief pattern satisfying this criterion provides a surface which is more or less planar from the viewpoint of the capability of said surface to serve as a substrate surface onto which a very thin insulating layer can be applied in a practical manner.
The FET obtained by employing (preferred embodiments of) the method in accordance with the invention is a top gate field-effect transistor. However, it will be obvious to those skilled in the art that if a bottom gate field-effect transistor is desired, the method in accordance with the invention is simply modified in that the gate electrode is accommodated by the first and the source and drain electrodes are accommodated by the second electrode layer, and the semiconducting and electrically insulating layer are applied in reverse order. Yet another bottom gate FET is obtained if the method of manufacturing the bottom gate FET is modified in that the second electrode and semiconducting layer are applied in reverse order.
The invention also relates to a field-effect transistor substantially consisting of organic materials, that is a field-effect transistor comprising a stack of:
an organic first electrode layer accommodating a source and drain electrode and demonstrating a relief pattern of electrically conducting areas,
an organic semiconducting layer,
an organic electrically insulating layer, and
an organic second electrode layer accommodating a gate electrode.
The remarkable observation, described hereinabove, that the presence of a relief patterned first electrode layer does not lead to large leakage currents between the source (drain) and gate electrode if the thickness of this layer is less than that of the insulating layer, remains valid regardless of the method of preparing the relief pattern. In accordance with the invention, the field-effect transistor is therefore characterized in that the thickness of the electrically insulating layer is greater than the thickness of the first and/or second electrode layer and less than 0.3 xcexcm. It is clear that applying a 0.3 xcexcm layer on a 0.3 xcexcm topography results in an insulating layer which is neither planar nor planarized. Surprisingly, the use of planarised insulating layers appears to be superfluous. Short circuits are substantially absent if the surface defined by the first and/or second electrode layer has a topography smaller than the layer thickness of the insulating layer to be applied to that surface. In order to satisfy the condition for voltage amplification at a source drain voltage difference below 10 V, the insulating layer should have a thickness less than 0.3 xcexcm. Since the insulating layer may be far from planar, the layer thickness is defined as the thickness that would have been obtained if, using the same method, it had been applied onto a planar surface.
In the Japanese Patent Application JP-A-1-259563, a field-effect transistor substantially consisting of organic materials is disclosed. Said document does not disclose a method of manufacturing such a device, let alone a practical method producing a field-effect transistor which satisfies the condition for voltage amplification below a source drain voltage of 10 V. The known field-effect transistor does not have a patchwork patterned electrode layer and the thickness of the planarized insulating layer is not specified.
The invention also relates to an integrated circuit comprising a field-effect transistor in accordance with the invention or a field-effect transistor obtainable by a method in accordance with the invention. Changing the pattern of the first and second electrode layer is all that needs to be done if not just one but a plurality of organic FETs is to be produced on a single substrate surface.